FPGA / RISC-V / Digital Design

Kumagai Daichi Portfolio

View Projects GitHub

boot_portfolio.sh

$ load profile
[OK] profile.json
$ compile projects
[OK] fpga_piano.v
[OK] minesweeper_solver.c
$ render portfolio
$ echo "$WELCOME"
Welcome — enjoy the build 👋
█

profile.json

{
  "name": "Daichi Kumagai",
  "school": "Institute of Science Tokyo, Computer Science",
  "lab": "Kise Laboratory",
  "focus": [
    "FPGA",
    "RISC-V",
    "Digital Circuit Design"
  ],
  "contact": "kumagai.d.1e80@m.isct.ac.jp",
  "github": "kumagai0212"
}

Profile

Daichi Kumagai 熊谷大智

Hello, I am Daichi Kumagai, a 3rd-year student at Institute of Science Tokyo. After graduating from National Institute of Technology, Hachinohe College, I am now a member of the Kise Laboratory and continue learning hardware design every day.

Contact kumagai.d.1e80@m.isct.ac.jp

GitHub github.com/kumagai0212

background.yaml

background:
  - date: 2019/04
    event: Entered NIT, Hachinohe College
  - date: 2024/03
    event: Graduated from NIT, Hachinohe College
  - date: 2024/04
    event: Transferred to Tokyo Institute of Technology
  - date: 2025/04
    event: Joined Kise Laboratory

certifications:
  - Applied Information Technology Engineer Examination
  - Fundamental Information Technology Engineer Examination
  - TOEIC 830

Background

Background & Certifications

2019/4

Entered the Electrical and Computer Engineering Course, Department of Industrial Systems Engineering, National Institute of Technology, Hachinohe College

2024/3

Graduated from the Electrical and Computer Engineering Course, Department of Industrial Systems Engineering, National Institute of Technology, Hachinohe College

2024/4

Transferred to the Department of Computer Science, School of Computing, Tokyo Institute of Technology

2025/4

Joined Kise Laboratory

Applied Information Technology Engineer Examination (Spring 2025) Fundamental Information Technology Engineer Examination (2024/7/12) TOEIC 830 (2024/1/28)

publication.bib

@inproceedings{robbit2025,
  title  = {Robbit: A User-Friendly and
            Two-Wheeled Self-Balancing Robot
            Using an FPGA},
  author = {Daichi Kumagai and Yuya Iwata
            and Komei Kodera and Kenji Kise},
  booktitle = {IEEE MCSoC},
  year = {2025}
}

Publications

Robbit: A User-Friendly and Two-Wheeled Self-Balancing Robot Using an FPGA

2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)

Daichi Kumagai, Yuya Iwata, Komei Kodera, Kenji Kise

This work proposes “robbit,” a low-cost and user-friendly two-wheeled self-balancing robot using an FPGA. By using a RISC-V soft-core processor and the CFU Proving Ground framework, we designed and implemented it as an educational platform for learning hardware, gateware, and software co-design.

Publisher Link (DOI)

Projects

fpga_piano.v

module fpga_piano_tiles (
  input  wire clk,
  input  wire [3:0] button,
  output wire spi_sck,
  output wire spi_mosi
);

  xorshift32 note_randomizer();
  vram_controller lcd_renderer();
  difficulty_controller speed_up();

endmodule

FPGA Piano Tiles

Device: Digilent Arty A7-35T
Language: Verilog HDL
Peripherals: ST7789 (240x240 LCD), Tactile Buttons

FPGA Piano Tiles is a rhythm game running on an FPGA board. I implemented a game system where notes fall through four lanes and the player presses the corresponding buttons with correct timing.

The entire logic is implemented in Verilog without using a processor. It includes random note generation using a 32-bit Xorshift generator, LCD drawing control over SPI, a custom VRAM management circuit, and dynamic difficulty adjustment that increases the note speed as the game progresses.

GitHub Repository

minesweeper_solver.c

while (!game_over) {
  human_open(cursor);
  update_visible_board();

  ai_move = solve_by_inference();
  if (!ai_move.safe) {
    ai_move = choose_lowest_risk_cell();
  }
  open_cell(ai_move);
  draw_to_lcd_and_vga();
}

Minesweeper Solver FPGA

Device: Digilent Nexys A7
Language: C, Verilog HDL
Peripherals: ST7789 (240x240 LCD), VGA, Buttons, 7-segment Display

This is a competitive Minesweeper game running on an FPGA board. A human player and an AI alternately open cells on the same board, and the side that opens a mine first loses.

The game logic runs on a RISC-V soft-core SoC based on CFU Proving Ground, and I added Verilog hardware for memory-mapped button input and 7-segment display output. The AI searches for safe cells using rule-based inference and risk evaluation. The system supports both ST7789 LCD and VGA output, and special cells add information asymmetry and turn-control mechanics.

GitHub Repository

experience.toml

[experience]
company = "Aratama Factory"
role = "FPGA Development Engineer"
period = "2025/05 - present"

skills = [
  "FPGA development",
  "Digital circuit design",
  "Beamforming",
  "Prompt engineering"
]

Experience

Aratama Factory

Website ↗

2025/5 - Present

FPGA Development Engineer (Part-time)

I work on hardware development using FPGAs. Although the details of the work are confidential, I mainly contribute to development and design in the following technical areas.

FPGA development Digital circuit design Beamforming Prompt engineering

skills.ts

type SkillSet = {
  languages: string[];
  hardware: string[];
  tools: string[];
};

const skills: SkillSet = {
  languages: ["Verilog", "SystemVerilog", "C/C++", "Python"],
  hardware: ["Artix-7", "RISC-V", "HLS", "I2C/SPI/UART"],
  tools: ["Vivado", "Vitis", "Git", "Linux"]
};

Skills

Languages

Verilog HDL
SystemVerilog
C / C++
Python
HTML / CSS

Hardware & FPGA

Xilinx Artix-7 (Arty, Cmod)
RISC-V Architecture
Digital Circuit Design
High-Level Synthesis (HLS)
I2C / SPI / UART

Tools & Others

Vivado / Vitis
Git / GitHub
Visual Studio Code
LaTeX
Linux